1. Field of the Invention
The present invention relates to a data control method and apparatus, and more particularly, to a data control method and apparatus in which the power consumed and heat generated in a data driving circuit can be reduced.
2. Background of the Related Art
There is a growing interest in flat panel display devices capable of reducing the weight and the volume of the display device as compared to a cathode ray tube (“CRT”). These flat panel display devices can include a liquid crystal display (“LCD”), a plasma display panel (“PDP”), a field emission display (“FED”), electro-luminescence (“EL”), and the like. These flat panel display devices supply a digital signal or analog data to the display panels.
Of these flat panel display devices, the PDP is adapted to display an image of characters or graphics using light-emitting phosphors excited by ultraviolet light of about 147 nm generated during the discharge of a gas, for example, He+Xe, Ne+Xe or He+Ne+Xe. A PDP can easily be made large and thin, and with the recent development of the relevant technology, it can provide great increases in image quality. Particularly, a three-electrode AC surface discharge type PDP has the advantages of lower driving voltage and longer product lifespan because wall charges accumulate on a surface upon discharge and the electrodes are protected from sputtering caused by discharge.
The three-electrode AC surface discharge type PDP is driven with one frame being time-divided into a plurality of sub-fields each having a different number of discharge in order to implement the gray scale of an image. Each of the sub-fields is divided into a reset period for uniformly generating discharge, an address period for selecting a discharge cell, and a sustain period for implementing the gray level according to the number of discharges. To display an image with a gray scale of 256, a frame period corresponding to 1/60 seconds (16.67 ms) is divided into eight sub-fields SF1 to SF8, as shown in FIG. 1. Each of the sub-fields SF1 to SF8 is subdivided into the reset period, the address period, and the sustain period, as described above. The reset period and the address period of each of the sub-fields SF1 to SF8 are the same in every sub-field, and the sustain period and the frequency of its discharge number increase by the ratio of 2n (n=0, 1, 2, 3, 4, 5, 6, 7) in each sub-field. Accordingly, as the sustain period varies in every sub-field, the gray scale of an image can be implemented.
In a PDP, however, since a driving voltage is relatively high due to a discharge characteristic that causes discharge to occur between two electrodes and the large size of the panel, the resulting power consumption is relatively high. Furthermore, a driver integrated circuit (“IC”) for driving data electrodes and scan electrodes of the PDP must supply a high voltage to electrodes Y, Z and X, respectively, in order to generate discharge. Therefore, the power consumed and heat generated are relatively high.
In a PDP, power is primarily consumed in the sustain period and secondarily consumed in the address period. For example, the sustain period requires several hundreds of watts, and the address period requires several tens of watts. Power consumption of the sustain period primarily depends upon the efficiency of the PDP. Power consumption of the address period primarily depends upon a capacitance value C and voltage V of the PDP and the switching number of the driver IC.
The capacitance C of the PDP includes a capacitance C1 between data electrodes X1 to Xn, a capacitance C2 between the data electrodes X1 to Xn and scan electrodes Y1 to Ym, a capacitance C3 between the scan electrodes Y1 to Ym and a common sustain electrode Z, and a capacitance C4 between the address electrodes X and the common sustain electrode Z, as shown in FIG. 2. At least 90% of power consumed during the address period is a result of a displacement current occurring upon the charging/discharging of a PDP. The amount of the power consumed during the address period, which is generated by the displacement current, can be expressed by the following Equation 1:P=IV=CV2f  (1)
wherein I is current, V is voltage of a data pulse, C is a capacitance value between the address electrode X and other electrodes Y, Z adjacent to the electrode X, and f is an average switching number per time of a data driver IC expressed as a frequency.
As such, if an energy recovery circuit is adapted in the data driver IC, the power consumption of the data driver IC can be expressed by the following Equation 2:P=IV=CV2f(1−α)  (2)
wherein α is energy recovery efficiency by an energy recovery circuit. In the data driver IC, the energy recovery efficiency α is about 0.5 maximum.
As can be seen from Equations 1 and 2, methods for reducing the power consumed during the address period can include lowering the number of charging/discharging to lower displacement current I, lowering data voltage V, lowering capacitance C of a PDP, reducing the switching number f of a data driver IC, and the like. Lowering data voltage V, however, is a limited solution because the voltage can generate discharge in a discharge cell. Further, lowering capacitance C of a PDP is also a limited solution because the PDP has been developed toward higher resolution with a larger screen.
The switching number f of the data driver IC is highest when the data pattern has a logic High and a logic Low alternating in the discharge cells in both a column direction and a row direction, as shown in FIG. 3. In other words, the data pattern shown in FIG. 3 requires the data driver IC to repeatedly turn on and off a switching element every horizontal period.
If the switching element of the data driver IC repeatedly turns on and off every horizontal period, there are problems in that the power consumed is high and heat is generated in the data driver IC. Actually, if the data pattern as shown in FIG. 3 is consistently supplied for an extended time, extreme heat can be generated in the data driver IC, and the data driver IC can be damaged.
Moreover, the switching number f of the data driver IC is high when voltages of the same logic level are applied to two adjacent discharge cells 10, as shown in FIG. 4. In this pattern, a logic High and a logic Low alternate in discharge cells in a row direction and alternate in groups of two discharge cells in a column direction. In other words, the data driver IC repeats turning on and off a switching element every two horizontal periods for the data pattern, as shown in FIG. 4. Accordingly, the power consumed is high and too much heat is generated.
In addition, the capacitance C of a PDP is also high as a result of the data patterns shown in FIGS. 3 and 4. As can be seen from the above, in the data patterns shown in FIGS. 3 and 4, the capacitance of a PDP and the switching number of a data driver IC are both high. Therefore, since the displacement current is high, the power consumed and heat generated are relatively high.